1. Technical Field
The present invention relates to a test circuit for a data line driving circuit or a scanning line driving circuit of an electro-optical device using liquid crystal, to an electro-optical device having such a test circuit, and to an electronic apparatus having such an electro-optical device.
2. Related Art
In the related art, electro-optical devices, such as liquid crystal display devices for displaying images, are known. An electro-optical device has, for example, a liquid crystal panel, and a driving circuit for driving the liquid crystal panel. In such an electro-optical device, in order to check the operations of the driving circuit, there is provided a test circuit which checks the operations of the driving circuit by hitting a test probe (see Japanese Patent No. 3203971). Such an electro-optical device has, for example, the following configuration.
Overall Configuration of Electro-Optical Device
FIG. 14 is a block diagram showing the configuration of an electro-optical device 101 according to the related art.
The electro-optical device 101 has a liquid crystal panel AA, a power supply circuit 2 which supplies power to the liquid crystal panel AA, an image processing circuit 3 which supplies image signals to the liquid crystal panel AA, and a timing generating circuit 4 which outputs clock signals or start signals to the image processing circuit 3 or the liquid crystal panel AA.
The power supply circuit 2 supplies driving signals VDDY, VSSY, VHHY, VLLY, VDDX, VSSX, VHHX, and VLLX to the liquid crystal panel AA.
The image processing circuit 3 performs the gamma (γ) correction on input image data D in consideration of light transmittance characteristics of the liquid crystal panel, generates the image signals by performing the D/A conversion of image data D of individual RGB colors, and supplies the image signals to the liquid crystal panel AA.
The timing generating circuit 4 generates a Y clock signal YCK, an inverted Y clock signal YCKB, an X clock signal XCK, an inverted X clock signal XCKB, a Y transmission start signal DY, and an X transmission start signal DX in synchronization with input image data D input to the image processing circuit 3.
The timing generating circuit 4 supplies the Y transmission start signal DY, the Y clock signal YCK, and the inverted Y clock signal YCKB of these signals to a scanning line driving circuit 20 (described below) of the liquid crystal panel AA. Further, the timing generating circuit 4 supplies the X transmission start signal DX, the X clock signal XCK, and the inverted X clock signal XCKB to a data line driving circuit 30 (described below) of the liquid crystal panel AA. In addition, the timing generating circuit 4 generates various timing signals and outputs them to the image processing circuit 3.
The liquid crystal panel AA has an element substrate on which thin film transistors (hereinafter, referred to as TFTs) 13 are arranged in a matrix shape as switching elements, a counter substrate which is disposed to face the element substrate, and liquid crystal which is provided between the element substrate and the counter substrate.
On the element substrate of the liquid crystal panel AA, in addition to a pixel matrix 10, the scanning line driving circuit 20, and the data line driving circuit 30, test circuits 121 and 131 are formed.
In the pixel matrix 10, a plurality of scanning lines 11 provided at predetermined intervals, and data lines 12 provided to intersect the scanning lines 11 at predetermined intervals are formed. At each of the intersections between the scanning lines 11 and the data lines 12, the TFT 13, a pixel electrode 14, and a storage capacitor 15 are provided.
A gate of the TFT 13 is connected to the scanning line 11, a source of the TFT 13 is connected to the data line 12, and a drain of the TFT 13 is connected to the pixel electrode 14.
Each pixel has the pixel electrode 14, a counter electrode 16 formed on the counter substrate, and liquid crystal 17 provided between both electrodes. Accordingly, in the pixel matrix 10, a plurality of pixels are arranged in a matrix shape.
The scanning line driving circuit 20 drives the individual scanning lines 11 of the pixel matrix 10, and the data line driving circuit 30 drives the individual data lines 12 of the pixel matrix 10.
Specifically, the scanning line driving circuit 20 sequentially transmits the Y transmission start signal DY in synchronization with the Y clock signal YCK and the inverted Y clock signal YCKB, such that scanning signals are linear-sequentially applied to the individual scanning lines 11 in a pulsed manner. Therefore, if the scanning signal is supplied to a scanning line 11, the TFT 13 connected to the scanning line 11 is turned on, and all pixels relating to the scanning line 11 are selected.
Further, the data line driving circuit 30 sequentially transmits the X transmission start signal DX as a trigger signal in synchronization with the X clock signal XCK and the inverted X clock signal XCKB. Accordingly, the image signals are sequentially supplied to the individual data lines 12, and are sequentially written into the pixel electrodes 14 of the pixels through the TFT 13 which is in the ON state. The voltage of each pixel electrode 14 is held by the storage capacitor 15 for a longer time, namely, for a period as much as three orders of magnitude longer than the time for which the image signal is written.
Here, by changing the voltage level of the image signal, the alignment or order of liquid crystal changes according to the applied voltage, such that gray-scale display by light modulation of each pixel can be performed. For example, in case of a normally white mode, the amount of light passing through liquid crystal decreases as the applied voltage increases. In case of a normally black mode, as the applied voltage increases, the amount of light passing through liquid crystal increases. Therefore, in the liquid crystal panel AA, light having contrast according to the image signal is emitted from each pixel, such that the image is displayed.
Configuration of Driving Circuit
FIG. 15 is a circuit diagram of the data line driving circuit 30 and the test circuit 131 constituting the liquid crystal display device 101 according to the related art.
The data line driving circuit 30 is a shift register which has n shift register unit circuits A1 to An and n−1 logical arithmetic unit circuits B1 to B(n−1). Here, n is a natural number of 2 or more. Moreover, the scanning line driving circuit 20 has the same configuration as that of the data line driving circuit 30.
Each of the shift register unit circuits A1 to An has first and second clocked inverters 71 and 72, and an inverter 73. The output ends of the first and second clocked inverters 71 and 72 are connected to the input end of the inverter 73, and the output end of the inverter 73 is connected to the input end of the second clocked inverter 72.
One of the X clock signal XCK and the inverted X clock signal XCKB is supplied to the control terminal of the first clocked inverter 71, and the other is supplied to the control terminal of the second clocked inverter 72.
Therefore, if the X transmission start signal DX is set to be active at the H level is supplied to the data line driving circuit 30, the shift register unit circuits A1 to An transmit the X transmission start signal DX in synchronization with the clock signals XCK and XCKB so as to output a pulse signal to the test signal 131 and to output the output signals P1 to Pn to the logical arithmetic unit circuits B1 to B(n−1).
Each of the logical arithmetic unit circuits B1 to B(n−1) has a NAND circuit 51 which calculates the logical product, inverts the logical product, and outputs the inverted logical product, and an inverter circuit 52 which inverts the output signal from the NAND circuit 51. Specifically, the output signal Pm from the shift register unit circuit Am and the output signal P(m+1) from the shift register unit circuit A(m+1) are input to the logical arithmetic unit circuit Bm (for example, m is a natural number of n−1 or less). The logical arithmetic unit circuit Bm calculates the logical product of the output signal Pm and the output signal P(m+1) and outputs the logical product as the sampling signal Smm.
Therefore, the logical arithmetic unit circuits B1 to B(n−1) individually generate the sampling signals Sm1 to Sm(n−1) on the basis of the output signals P1 to Pn from the shift register unit circuits A1 to An.
The test circuit 131 is a buffer circuit in which inverter circuits 61, 62, 63, and 64 are connected in series. The test circuit 131 amplifies the pulse signal from the data line driving circuit 30 and outputs an output signal XEP. Therefore, by hitting the test probe against the test circuit 131, the output signal XEP is detected, and it is checked that the data line driving circuit 30 reliably operates. Moreover, the test circuit 121 has the same configuration as that of the test circuit 131.
However, the data line driving circuit 30 outputs the pulse signal whenever the images of one frame are displayed. According to this configuration, transistors constituting the inverter circuits 61 to 64 of the test circuit 131 are repeatedly turned on and off by the pulse signal. Whenever the transistor is turned on, a breakthrough current is generated, capacitance of the transistors or wiring lines is charged, and thus power consumes. Accordingly, there is a problem in that, after the operation check, at the time of normal driving, power consumption of the test circuit 131 increases. Further, the same problem occurs in the scanning line driving circuit 20.